A critical parameter in memories and particularly nonvolatile memories like flash memories is the access time to access data. When reading randomly from a memory core such an access is defined as an asynchronous access, (defined as Tace, data valid from a chip enable complement CE* transition). When reading data there can be spurious glitches on the data connections (DQs), which can usually be filtered out at the expense of increasing data access time.
Referring to FIGS. 1 and 2, which are a block diagram of a memory and a timing diagram of data passing from the memory, the access time Tace is driven by three main circuit blocks, the memory core 102, data path component 104, and output buffer component 106. Memory core 102 contains a memory array 108, sense amplifiers 110, address transition detector (atd) and read timer 112, and latch 114. Data path component 104 contains data path driver 116 and latch 118. Output buffer component 106 contains output buffers 120. The memory core 102 with the sense amplifiers 110, sets the amount of time needed from supply of signal CE*=0 to select the addressed location, to sense the data from the array 108 and have the data ready and presented at the memory bank boundary. The data path circuit 104 controls data propagation through the memory 100 up to the pad area and the output buffers 120 are used to drive the output load.
Typically, the output buffers 120 are set as pass through buffers at the beginning of the read phase, allowing an immediate transition as soon as the internal data is read from the array 108 and propagated through the data path 104. The delay, as shown in FIG. 2, is Δτ0. Such approach has the side effect of making the output buffers transparent to any transition of the data path even when the data are not valid yet. The architecture of the data path drives the timing and number of such undesired spurious transitions (FIGS. 1-2).
In working with very fast memories, it is desirable to decrease the time data takes to propagate from the sense amplifiers to the output buffers. One way to do this is to keep all data communications from the sense amplifiers to the output buffers transparent. When new data is detected at the sense amplifiers, it propagates to the output buffers. This allows for a minimum time delay from the sense amplifiers to the output buffers. However, the sense amplifiers in reading data from the array generate spurious data outputs before stabilization to valid data. This spurious data output propagates to the output buffers as noise before stabilization. There is a minimum time delay Δτ0 that data takes to move from the input of the data path driver 116 to the output from data path latch 118. When access time Tace is set for the device 100, then, the specification for the device indicates that the data are not valid until expiration of the minimum access time Tace. Spurious data cannot be considered good data until the access time expires. While such an approach is very fast, the transitions in the spurious data greatly increase memory power consumption because of the switching of the output buffers. This current consumption without information is inconvenient for customers and consumes power, which is in increasingly short supply in today's memories.
To avoid the spurious output switching of the configuration shown in FIG. 1, a conventional approach to the problem of spurious output transitions is shown in FIG. 3, and is based on the use of a second atd and read timer circuit 202 which takes the same inputs as the atd and read timer 112 of memory 100, to generate a signal (sa_latch_filter in FIG. 3) to mask all of the internal data path transitions immediately before the output buffer drivers 120. This signal enables the output buffers 120 only after the data are stable, by opening keeping latch 118 closed until the signal has propagated through atd and read timer 202, and opening latch 118 at that time. The calculated time is longer than Tace minimum by a margin, Tm. The margin Tm is added to the minimum Tace to cover the time needed to enable the latch.
The approach of FIG. 3 uses the margin Tm to allow the signal to cut all of the undesired spurious data transitions. This time Tm must allow sufficient propagation time based on the maximum expected time to eliminate all possibility of spurious transitions. Defining the value for Tm requires an accurate evaluation of two parameters, the addressed data sensing time and the data propagation delay to the output buffers. Both parameters depend upon process spread, architecture, layout and memory size, and therefore some estimation is required. To avoid the possibility of invalid data at the output buffers, the margin Tm is increased to a safe time. The uncertainty about these parameters evaluation drives the Tm value up.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for apparatus and techniques for filtering spurious data output but increasing speed of access.